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ordering number : en * 5085a 32896ha (ot)/33195th (ot) no. 5085-1/29 overview the LC322271J, m and t is a cmos dynamic ram operating on a single 5 v power source and having a 131072 words 16 bits configuration. equipped with large capacity capabilities, high speed transfer rates and low power dissipation, this series is suited for a wide variety of applications ranging from computer main memory and expansion memory to commercial equipment. address input utilizes a multiplexed address bus which permits it to be enclosed in a compact plastic package of soj 40-pin, sop 40-pin, and tsop 44-pin . refresh rates are within 8 ms with 512 row address (a0 to a7, a8r) selection and support row address strobe (ras)-only refresh, column address strobe (cas)-before-ras refresh and hidden refresh settings. there are functions such as fast page mode, read-modify-write and byte write. the pin assignment follows the jedec 1 m dram (65536 words 16 bits, 1cas/2we) standard. features 131072 words 16 bits configuration. single 5 v 10% power supply. all input and output (i/o) ttl compatible. supports fast page mode, read-modify-write and byte write. supports output buffer control using early write and output enable (oe) control. 8 ms refresh using 512 refresh cycles. supports ras-only refresh, cas-before-ras refresh and hidden refresh. follows the jedec 1 m dram (65536 words 16 bits, 1cas/2we) standard. ras access time/column address time/cas access time/cycle time/power dissipation package: soj 40-pin (400 mil) plastic package : LC322271J sop 40-pin (450 mil) plastic package: lc322271m tsop 44-pin (400 mil) plastic package : lc322271t package dimensions unit: mm 3200-soj40 preliminary sanyo: soj40 [LC322271J] LC322271J, m, t-70/80 sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-0005 japan 2 meg (131072 words 16 bits) dram fast page mode, byte write cmos lsi parameter LC322271J, m, t -70 -80 ras access time 70 ns 80 ns column address access time 35 ns 45 ns cas access time 20 ns 30 ns cycle time 130 ns 150 ns power dissipation (max.) during operation 688 mw 633 mw during standby 5.5 mw (cmos level)/11 mw (ttl level)
p ac ka g e dimensions unit: mm 3195-sop40 pin assignments no. 5085- 2 /29 LC322271J, m, t-70/80 sanyo: sop40 [lc322271m] unit: mm 3207-tsop44 sanyo: tsop44 (type ii) [lc322271t]
block diagram specifications absolute maximum ratings note: 1. stresses greater than the above listed maximum values may result in damage to the device. no. 5085- 3 /29 LC322271J, m, t-70/80 parameter symbol ratings unit note maximum supply voltage v cc max ?.0 to +7.0 v 1 input voltage v in ?.0 to +7.0 v 1 output voltage v out ?.0 to +7.0 v 1 allowable power dissipation LC322271J, m pd max 800 mw 1 lc322271t 700 output short-circuit current i out 50 ma 1 operating temperature range topr 0 to +70 c 1 storage temperature range tstg ?5 to +150 c 1
dc recommended operating ranges at ta = 0 to +70 c note: 2. all voltages are referenced to v ss . * : ?.0 v when pulse width is less than 20 ns. dc electrical characteristics at ta = 0 to +70 c, v cc = 5 v 10% note: 3. all current values are measured at minimum cycle rate. since current flows immoderately, if cycle time is longer than shown her e, current value becomes smaller. 4. i cc1 and i cc4 are dependent on output loads. maximum values for i cc1 and i cc4 represent values with output open. 5. address change is less than or equal to one time during ras = v il . concerning i cc4 , it is less than or equal to one time during 1 cycle (t pc ). ac electrical characteristics at ta = 0 to +70 c, v cc = 5 v 10% (notes 6, 7 and 8) no. 5085- 4 /29 LC322271J, m, t-70/80 parameter symbol min typ max unit note power supply voltage v cc 4.5 5.0 5.5 v 2 input high level voltage v ih 2.4 6.5 v 2 input low level voltage v il ?.0 * +0.8 v 2 (a0 to a7, a8r, ras, cas, uw, lw, oe) input low level voltage (i/o1 to i/o16) v il ?.5 * +0.8 v 2 parameter symbol -70 -80 unit note min max min max random read, write cycle time t rc 130 150 ns read-write/read-modify-write cycle time t rwc 190 200 ns fast page mode cycle time t pc 45 55 ns fast page mode read-write/read-modify-write cycle time t prwc 95 100 ns ras access time t rac 70 80 ns 9, 14, 15 cas access time t cac 20 30 ns 9, 14 column address access time t aa 35 45 ns 9, 15 cas precharge access time t cpa 40 50 ns 9 output low-impedance time from cas low t clz 0 0 ns 9 output buffer turn-off delay time t off 0 20 0 20 ns 10 rise, fall time t t 3 50 3 50 ns ras precharge time t rp 50 60 ns ras pulse width t ras 70 10000 80 10000 ns ras pulse width for fast page mode cycle only t rasp 70 100000 80 100000 ns continued on next page. LC322271J, m, t parameter symbol conditions -70 -80 unit note min max min max operating current i cc1 ras, cas, address cycling: t rc = t rc min 125 115 ma 3, 4, 5 (average current during operation) standby current i cc2 ras = cas = v ih 2 2 ma ras-only refresh current i cc3 ras cycling, cas = v ih : t rc = t rc min 125 115 ma 3, 5 fast page mode current i cc4 ras = v il , cas, address cycling: t pc = t pc min 115 90 ma 3, 4, 5 standby current i cc5 ras = cas = v cc ?0.2 v 1 1 ma cas-before-ras refresh current i cc6 ras, cas cycling: t rc = t rc min 125 115 ma 3 input leakage current i il 0 v v in 6.5 v, pins other than test pin = 0 v ?0 +10 ?0 +10 a output leakage current i ol d out disable, 0 v v out 5.5 v ?0 +10 ?0 +10 a output high level voltage v oh i out = ?.5 ma 2.4 2.4 v output low level voltage v ol i out = 2.1 ma 0.4 0.4 v
continued from preceding page. no. 5085- 5 /29 LC322271J, m, t-70/80 -70 -80 parameter symbol min max min max unit note ras hold time t rsh 20 30 ns cas hold time t csh 70 80 ns cas pulse width t cas 20 10000 30 10000 ns ras to cas delay time t rcd 25 50 25 50 ns 14 ras to column address delay time t rad 17 35 17 35 ns 15 cas to ras precharge time t crp 10 10 ns cas precharge time t cp 10 10 ns row address setup time t asr 0 0 ns row address hold time t rah 12 12 ns column address setup time t asc 0 0 ns column address hold time t cah 15 20 ns column address hold time referenced to ras t ar 50 60 ns column address to ras lead time t ral 40 45 ns read command setup time t rcs 0 0 ns read command hold time referenced to cas t rch 0 0 ns 11 read command hold time referenced to ras t rrh 0 0 ns 11 write command hold time t wch 15 15 ns write command hold time referenced to ras t wcr 50 60 ns write command pulse width t wp 15 15 ns write command to ras lead time t rwl 25 25 ns write command to cas lead time t cwl 20 20 ns data input setup time t ds 0 0 ns 12 data input hold time t dh 15 20 ns 12 data input hold time referenced to ras t dhr 50 60 ns refresh time t ref 8 8 ms write command setup time t wcs 0 0 ns 13 cas to uw, lw delay time t cwd 50 50 ns 13 ras to uw, lw delay time t rwd 100 100 ns 13 column address to uw, lw delay time t awd 65 65 ns 13 cas precharge uw, lw delay time for fast page mode t cpwd 70 70 ns 13 cycle only cas setup time for cas-before-ras t csr 10 10 ns cas hold time for cas-before-ras t chr 15 15 ns ras precharge cas active time t rpc 10 10 ns cas precharge time for cas-before-ras counter test t cpt 40 40 ns ras hold time referenced to oe t roh 15 15 ns oe access time t oea 20 25 ns 9 oe delay time t oed 15 15 ns oe output buffer turn-off delay time t oez 0 0 15 ns 10 oe command hold time t oeh 20 20 ns data input to cas delay time t dzc 0 0 ns 16 data input to oe delay time t dzo 0 0 ns 16 masked write setup time t mcs 0 0 ns masked write hold time referenced to ras t mrh 0 0 ns masked write hold time referenced to cas t mch 0 0 ns
input/output capacitance at ta = 25 c, f = 1 mhz, v cc = 5 v 10% note: 6. an initial pause of 200 s is required after power-up followed by eight ras-only refresh cycles before proper device operation is achieved. in case of using refresh counter, a minimum of eight cas-before-ras refresh cycles instead of eight ras-only refresh cycles are require d. 7. measured at t t = 5 ns. 8. when measuring input signal timing, v ih (min) and v il (max) are used for reference points. in addition, rise and fall time are defined between v ih and v il . 9. measured using an equivalent of 50 pf and one standard ttl loads. 10. t off (max) and t oez (max) are defined as the time until output voltage can no longer be measured when output switches to a high impedance condition. 11. operation is guaranteed if either t rrh or t rch is satisfied. 12. these parameters are measured from the falling edge of cas for an early-write cycle, and from the falling edge of uw and lw for a read- write/read-modify-write cycle. 13. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters for memory in that they specify the operating mode. if t wcs 3 t wcs (min), the cycle switches to an early-write cycle and output pins switch to high impedance throughout the cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min) for fast page mode cycle only, the cycle switches to a read-write/read-modify-write cycle and data output equal information in the selected cells. if neither of the above timings are satisfied, output pins are in an undefined state. 14. t rcd (max) is not a restrictive operating parameter but instead represents the point at which the access time t rac (max) is guaranteed. if t rcd 3 t rcd (max), access time is determined according to t cac . 15. t rad (max) is not a restrictive operating parameter but instead represents the point at which the access time t rac (max) is guaranteed. if t rad 3 t rad (max), access time is determined according to t aa . 16. operation is guaranteed if either t dzc or t dzo i s satisfied. no. 5085- 6 /29 LC322271J, m, t-70/80 parameter symbol min max unit note input capacitance (a0 to a7, a8r, ras, cas, uw, lw, oe) c in 7 pf input/output capacitance (i/o1 to i/o16) c i/o 7 pf
timing chart read cycle no. 5085- 7 /29 LC322271J, m, t-70/80
early write cycle no. 5085- 8 /29 LC322271J, m, t-70/80
upper byte early write cycle no. 5085- 9 /29 LC322271J, m, t-70/80
lower byte early write cycle no. 5085- 10 /29 LC322271J, m, t-70/80
write cycle (oe control) no. 5085- 11 /29 LC322271J, m, t-70/80
upper byte write cycle (oe control) no. 5085- 12 /29 LC322271J, m, t-70/80
lower byte write cycle (oe control) no. 5085- 13 /29 LC322271J, m, t-70/80
read-modify-write cycle no. 5085- 14 /29 LC322271J, m, t-70/80
read-modify upper byte write cycle no. 5085- 15 /29 LC322271J, m, t-70/80
read-modify lower byte write cycle no. 5085- 16 /29 LC322271J, m, t-70/80
fast page mode read cycle no. 5085- 17 /29 LC322271J, m, t-70/80
fast page mode early write cycle no. 5085- 18 /29 LC322271J, m, t-70/80
fast page mode upper byte early write cycle no. 5085- 19 /29 LC322271J, m, t-70/80
fast page mode lower byte early write cycle no. 5085- 20 /29 LC322271J, m, t-70/80
fast page mode read-modify-write cycle no. 5085- 21 /29 LC322271J, m, t-70/80
fast page mode read-modify upper byte write cycle no. 5085- 22 /29 LC322271J, m, t-70/80
fast page mode read-modify lower byte write cycle no. 5085- 23 /29 LC322271J, m, t-70/80
hidden refresh cycle no. 5085- 24 /29 LC322271J, m, t-70/80
ras-only refresh cycle cas-before-ras refresh cycle no. 5085- 25 /29 LC322271J, m, t-70/80
cas-before-ras refresh counter test cycle (read) no. 5085- 26 /29 LC322271J, m, t-70/80
cas-before-ras refresh counter test cycle (write) no. 5085- 27 /29 LC322271J, m, t-70/80
cas-before-ras refresh counter test cycle (read-modify-write) no. 5085- 28 /29 LC322271J, m, t-70/80
ps no. 5085- 29 /29 LC322271J, m, t-70/80 this catalog provides information as of march, 1996. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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